1 About this specification

Chapter 1 About this specification 1.1 References This specification refers to the following documents: [1] PCI Express® Base Specification Revision 6.0. PCI-SIG. [2] Arm® Architecture Reference Manual for A-profile architecture. (ARM DDI 0487) Arm Ltd. [3] Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for A-profile architecture. (ARM DDI 0598) Arm Ltd. [4] Arm® System Memory Management Unit, SMMU architecture version 2.0. (ARM IHI 0062) Arm Ltd. [5] TDISP eXtended TEE (XT) Extensions. PCI-SIG. [6] Compute Express Link Specification. (Revision 1.1) CXL Contractual SIG. [7] Arm® Generic Interrupt Controller, GIC architecture version 3.0 and version 4.0. (ARM IHI 0069) Arm Ltd. [8] AMBA® AXI and ACE Protocol Specification. (ARM IHI 0022) Arm Ltd. [9] IO Remapping Table Platform Design Document. (ARM DEN 0049) Arm Ltd. [10] Arm® CoreSight ™Architecture Specification 3.0. (ARM IHI 0029) Arm Ltd. [11] Arm® Reliability, Availability, and Serviceability (RAS) System Architecture. (ARM IHI 0100) Arm Ltd. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 17

Chapter 1. About this specification 1.1. References [12] Arm® Base System Architecture 1.1. ARM DEN 0094D. [13] Arm® Server Base System Architecture. (ARM DEN 0029) Arm Ltd. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 18

Chapter 1. About this specification 1.2. Terms and abbreviations 1.2 Terms and abbreviations This specification uses the following terms and abbreviations. ASID Address Space ID, distinguishing TLB entries for separate address spaces. For example, address spaces of PE processes are distinguished by ASID. ATOS SMMU facility providing VA-to-IPA/PA translations using system-accessible registers. In addition, VATOS provides a second set of registers for direct use from a virtual machine, with the added constraint that only VA-to-IPA translations can be returned. ATS PCI Express [1] term for Address Translation Services provided for remote endpoint TLBs ATS Translated transaction A memory transaction input to the SMMU, in which the supplied address has been translated. In PCIe this is indicated with the AT TLP field value 0b10. For more information see 3.9 Support for PCI Express, PASIDs, PRI, and ATS. Bypass A configuration that passes through a stage of translation without any addresses transformation is using bypass. If an SMMU does not implement a translation stage, that stage is considered equivalent to a bypass configuration. CD Context Descriptor. Client device A device whose incoming traffic to the system is controlled by an SMMU. Completer An agent in a computing system that responds to and completes a memory transaction that was initiated by a Requester. CONSTRAINED UNPREDICTABLE Where an instruction can result in UNPREDICTABLE behavior, the architecture specifies a narrow range of permitted behaviors. This range is the range of CONSTRAINED UNPREDICTABLE behavior. All implementations that are compliant with the architecture must follow the CONSTRAINED UNPREDICTABLE behavior. In body text, the term CONSTRAINED UNPREDICTABLE is shown in SMALL CAPITALS. DVM Distributed Virtual Memory, a protocol for interconnect messages to provide broadcast TLB maintenance operations (among other things). E2H EL2 Host Mode. The Virtualization Host Extensions in Armv8.1 [2] extend the EL2 translation regime providing ASID-tagged translations. In this specification, EL2-E2H mode is the abbreviation that is used. EI Embedded Implementation. For more information see 3.16 Embedded Implementations. Endpoint (EP) A PCI Express [1] function, used in the context of a device that is a client of the SMMU. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 19

Chapter 1. About this specification 1.2. Terms and abbreviations GPC Granule Protection Check GPC fault A Granule Protection Check fault, arising either because a Granule Protection Table lookup could not be completed, or because the lookup was successful and the access being checked failed the check. GPF Granule Protection Fault. The fault reported when a Granule Protection Table lookup is successful, but the access being checked fails the Granule Protection Check. GPT Granule Protection Table. An in-memory structure that describes the association of a Location and a PA space. HTTU Hardware Translation Table Update. The act of updating the Access flag or dirty state of a page in a given descriptor which is automatically done in hardware, on an access or write to the corresponding page. IGNORED Indicates that the architecture guarantees that the bit or field is not interpreted or modified by hardware. In body text, the term IGNORED is shown in SMALL CAPITALS. ILLEGAL A set of conditions that make an STE or CD structure illegal. These conditions differ for the individual CDs and STEs, and are described in detail in the relevant CD and STE descriptions. A field in a structure can make the structure ILLEGAL, for example when it contains an incorrect value, only if the field was not IGNORED for other reasons. Attempts to use an ILLEGAL structure generate an error that is specific to the type of structure. IMPLEMENTATION DEFINED Means that the behavior is not architecturally defined, but must be defined and documented by individual implementations. For more information, see [2]. In body text, the term IMPLEMENTATION DEFINED is shown in SMALL CAPITALS. IMPLEMENTATION SPECIFIC Behavior that is not defined by the SMMU architecture, and might not be documented by individual implementations. Used where one of a number of implementation options might be chosen and the option chosen does not affect software compatibility. Software cannot rely on any IMPLEMENTATION SPECIFIC behavior. IPA Intermediate Physical Address L1CD Level-1 Context Descriptor. Used in a 2-level CD table. L1STD Level-1 Stream Table Descriptor. Used in a 2-level Stream table. LPAE Large Physical Address Extension. The ARMv7 ‘Long’ translation table format, supporting 40-bit output addresses (and 40-bit IPAs) and having 64-bit descriptors - identical to the VMSAv8-32 translation table format. MBZ Must Be Zero. Used in DPT descriptor formats. If a descriptor field described as MBZ is non-zero, the descriptor is Invalid. For more information, see 3.24.4 DPT lookup errors. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 20

Chapter 1. About this specification 1.2. Terms and abbreviations MPAM Memory System Resource Partitioning And Monitoring, part of the Armv8.4-A architecture [3]. Nested A configuration that enables both stage 1 and stage 2 translation. NoStreamID device An SMMU client device that is not associated with a StreamID. PA Physical Address PARTID, PMG MPAM partition and performance monitoring group identifiers. PASID PCI Express [1] term, a Process Address Space ID. Note: a PASID is an endpoint-local ID so there might be many distinct uses of a specific PASID value in a system. Despite the similarity in name, a PCIe PASID is not the same as a PE ASID, which is intended to be unique within the scope of an Operating System. PRI PCI Express term for Page Request Interface, an extension to ATS allowing an endpoint to request an OS to make a paged virtual memory mapping present for DMA. Processing Element (PE) The abstract machine defined in the Arm architecture, as documented in an Arm Architecture Reference Manual [2]. A PE implementation compliant with the Arm architecture must conform with the behaviors described in the corresponding Arm Architecture Reference Manual. RC PCI Express Root Complex [1] Requester An agent in a computing system that is capable of initiating memory transactions. RES0 A Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior, or equivalent read-only or write-only behavior. Used for fields in register descriptions, and for fields in architecturally-defined data structures that are held in memory, for example in translation table descriptors. For a full description see [2]. RES1 A Reserved bit or field with Should-Be-One-or-Preserved (SBOP) behavior. Used for fields in register descriptions, and for fields in architecturally-defined data structures that are held in memory, for example in translation table descriptors. For a full description see [2]. Reserved Unless otherwise specified, a Reserved field behaves as RES0. For an identification, or otherwise read-only register field, a Reserved encoding is never given by the SMMU. For a field that is provided to the SMMU, Reserved values must not be used and their behavior must not be relied upon. SEC_SID StreamID Security state. The identifer used to associate the StreamID in transactions from a client device with a specific Security state, and therefore determining which SMMU programming interface is responsible for configuration for the stream. See section 3.10.1 StreamID Security state (SEC_SID). ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 21

Chapter 1. About this specification 1.2. Terms and abbreviations SMMU System MMU. Unless otherwise specified, this term is used to mean SMMUv3. Any reference to prior versions of the SMMU specifications is explicitly suffixed with the architecture version number, for example SMMUv1. Split-stage ATS SMMU facility used with two-stage translation, providing a way to use ATS with stage 1 and use non-ATS translation for stage 2. Stage 1, Stage 2 One of the two stages of translation whereby the output of one set of translation tables can be fed into a second set of translation tables. In sequence, stage 1 is the first table indexed, stage 2 is the second. Each stage can be independently enabled. Stage 1 translates a VA to an IPA. Stage 2 translates an IPA to a PA. Stage N-only A translation configuration for a stream of data in which one of two translation stages is configured to translate and the other is in bypass (whether by configuration or fixed by SMMU implementation). STE Stream Table Entry. Terminate To complete a transaction with a negative status/abort response; the exact details depend on an implementation’s interconnect behavior. When a client transaction is said to have been terminated by the SMMU, it has been prevented from progressing into the system and an abort response has been issued to the client (if appropriate for the interconnect in use). TR Translation Request, used in the context of a PCIe ATS request to the SMMU, or another distributed implementation making translation requests to a central unit. TT Translation table, synonymous with Page Table, as used by Arm architecture. TTD Translation table descriptor , synonymous with Page Table Entry, as used by the Arm architecture TTW Translation Table Walk. This is the act of performing a translation by traversing the in-memory tables. UNKNOWN An UNKNOWN value does not contain valid data, and can vary from moment to moment and implementation to implementation. An UNKNOWN value must not return information that cannot be accessed at the current or a lower level of privilege of operating software using accesses that are not UNPREDICTABLE and do not return UNKNOWN values. An UNKNOWN value must not be documented or promoted as having a defined value or effect. In body text, the term UNKNOWN is shown in SMALL CAPITALS. UNPREDICTABLE Means the behavior cannot be relied upon. UNPREDICTABLE behavior must not perform any function that cannot be performed at the current or a lower level of privilege using instructions that are not UNPREDICTABLE. UNPREDICTABLE behavior must not be documented or promoted as having a defined effect. In body text, the term UNPREDICTABLE is shown in SMALL CAPITALS. Untranslated transaction. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 22

Chapter 1. About this specification 1.2. Terms and abbreviations A memory transaction input to the SMMU, in which the supplied address has not been translated. In PCIe this is indicated with the AT TLP field value 0b00. For more information see 3.9 Support for PCI Express, PASIDs, PRI, and ATS. VA Virtual Address VM Virtual Machine. In this specification, VM never means Virtual Memory except when used as part of an existing acronym. VMID Virtual Machine ID, distinguishing TLB entries for addresses from separate virtual machines VMS Virtual Machine Structure. Data structure containing per-VM information. 1.2.1 Inclusive Terminology Commitment Arm values inclusive communities. Arm recognizes that we and our industry have used terms that can be offensive. Arm strives to lead the industry and create change. Previous issues of this document included language that can be offensive. We have replaced this language. To report offensive language in this document, email terms@arm.com. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 23

Chapter 1. About this specification 1.3. Specification Scope 1.3 Specification Scope This specification is for a System Memory Management Unit version 3 following on from the previous SMMUv2 architecture [4]. This includes all the features from SMMUv3.0 to SMMUv3.5. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 24

Chapter 1. About this specification 1.4. Feedback 1.4 Feedback If you have any comments or queries about this Manual, create a ticket at https://support.developer.arm.com. As part of the ticket, include: • The title, Arm® System Memory Management Unit Architecture Specification, SMMU architecture version 3. • The number, ARM IHI 0070 H.a. • The section name to which your comments refer. • The page number(s) to which your comments refer. • A concise explanation of your comments. Arm also welcomes general suggestions for additions and improvements. Note Arm tests PDFs only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the appearance or behavior of any document when viewed with any other PDF reader. Search performance may be significantly improved by increasing the Fast Find Maximum Cache Size under Search in Preferences. If using Google Chrome™or Microsoft Edge™, load time is significantly improved since the April 2025 release of these browsers. Users may find, on some systems, that PDF viewers such as Okular or Foxit™give good performance. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 25