14 External interfaces¶
Chapter 14 External interfaces 14.1 Data path ingress/egress ports Along with read/write data/address, the following information is supplied with an incoming transaction: • StreamID • Optionally, SubstreamID (PASID) and a SubstreamID-Valid flag, SSV. • StreamID is qualified by a SEC_SID identifier to indicate the Security state of the StreamID. If the SMMU supports only Non-secure state, then SEC_SID might be absent and it is treated as always Non-secure. • StreamID is passed through the SMMU into the memory system, to create a DeviceID that enables the GICv3 ITS to differentiate interrupts by stream. – An internal StreamID is generated for MSIs originating from the SMMU. * Note: The StreamID generated for MSIs must have a different value to those associated with client devices, so that the GICv3 ITS can differentiate SMMU MSIs from those originating from client devices. • ATS Translated/Untranslated tag to control bypass. • Instruction/Data/NS permission attributes and Memory type/Shareability/allocation hints from upstream device (optional, can be overridden in STE). See Chapter 13 Attribute Transformation. If the ability to perform HTTU atomic updates using local monitors is required, the SMMU would need to attach to the system using a fully-coherent interconnect port. However, if HTTU is not implemented or the downstream system provides far atomic facilities which do not require a fully-coherent port, an IO-coherent interconnect port might be used. As the SMMU does not translate outgoing coherency or broadcast invalidation traffic, there is no requirement to ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1104
Chapter 14. External interfaces 14.1. Data path ingress/egress ports use an interconnect supporting cache coherency or DVM between the SMMU and client devices. Client devices might connect to the SMMU using an IO-coherent interconnect port. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1105
Chapter 14. External interfaces 14.2. ATS Interface, packets, protocol 14.2 ATS Interface, packets, protocol Note: An SMMU implementation might provide a separate interface to provide ATS and PRI protocol support with a compatible PCIe Root Complex. This interface is outside the scope of this specification. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1106
Chapter 14. External interfaces 14.3. SMMU-originated transactions 14.3 SMMU-originated transactions An SMMU read for any translation, configuration or queue structure that is performed into any PCIe address space is permitted to return any value or be terminated with an external abort. Note: Arm expects SMMU structures and translation tables that are accessed externally in non-embedded implementations to be located in system memory. A potential deadlock (where an SMMU read access is dependent on the completion of an incoming PCIe write which is itself dependent on the SMMU translation that caused the original access) can be avoided by the system terminating SMMU accesses targeted to the PCIe domain by malicious or incorrect software. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1107